About Me

I am currently a Postdoctoral Research Fellow at the University of California San Diego, advised by Prof. Gert Cauwenberghs. My research focuses on energy-efficient circuits and systems for artificial intelligence and combinatorial optimization.

My work spans energy-efficient memory and computing circuits for AI, circuit design automation, and heterogeneous photonic-electronic computing systems.

Appointments

  • 2024 - Present Postdoctoral Research Fellow, University of California San Diego
    Advisor: Prof. Gert Cauwenberghs
  • 2022 - 2024 Postdoctoral Research Fellow, Peking University
    Advisors: Prof. Xiyuan Tang, Prof. Yuan Wang, and Prof. Runsheng Wang

Education

  • 2017 - 2022 Ph.D. in Microelectronics, Peking University, Beijing, China
    Advisors: Prof. Runsheng Wang, Prof. Yuan Wang, and Prof. Xiyuan Tang
  • 2013 - 2017 B.S. in Electronic Science and Technology (Hons.), University of Electronic Science and Technology of China, Chengdu, China

Honors and Awards

  • Best Paper Award, IEEE/ACM Design, Automation and Test in Europe (DATE), 2023
  • Outstanding Postdoctoral Researcher, Peking University, 2023 (24 awardees university-wide)
  • Merit Student, Peking University, 2021
  • Outstanding Graduate Award, Sichuan Province, China, 2017
  • National Undergraduate Electronic Design Contest, Second Prize, 2016
  • National Undergraduate Electronic Design Contest, Second Prize, 2015

News

  • 2026: A paper on MixCIM appeared in IEEE Journal of Solid-State Circuits.
  • 2026: A CICC paper on a CIM-based annealing processor was selected.
  • 2025: Papers appeared in IEEE Journal of Solid-State Circuits on attention computing and Ising machines.
  • 2024: Began postdoctoral research at the University of California San Diego.
  • 2023: Received the DATE Best Paper Award.

Chip Gallery

Selected chips from first-author and co-first-author publications.

Analog-assisted digital compute-in-memory chip micrograph from JSSC 2026

Analog-Assisted Digital CIM

IEEE JSSC, 2026

Edge-pursuit continuous-time Ising machine chip micrograph, spin layout, and area breakdown from JSSC 2026

Edge-Pursuit Ising Machine

IEEE JSSC, 2026

MixCIM chip micrograph from CICC 2024

MixCIM Prototype

IEEE CICC, 2024

Variation-tolerant eDRAM continuous-time Ising machine die photo and summary from ISSCC 2024

Variation-Tolerant Ising Machine

IEEE ISSCC, 2024

Current-programmed 3T1C eDRAM compute-in-memory chip micrograph from CICC 2023 and JSSC 2024

Current-Programmed 3T1C eDRAM CIM

IEEE CICC, 2023 / IEEE JSSC, 2024

Spike-CIM macro micrograph and cell layout from A-SSCC 2022

Spike-CIM Macro

IEEE A-SSCC, 2022

3T eDRAM physically unclonable function chip micrograph from SSCL 2022

3T eDRAM PUF

IEEE SSCL, 2022

16 kb charge-domain transpose SRAM compute-in-memory chip micrograph and annotated layout from A-SSCC 2021 and TCAS-I 2023

Charge-Domain Transpose SRAM CIM

IEEE A-SSCC, 2021 / IEEE TCAS-I, 2023

TD-SRAM chip micrograph from TCAS-I 2021

TD-SRAM Macro

IEEE TCAS-I, 2021

Publications

Full citation record available on Google Scholar.

Journal Publications

  1. J1X Qiao, Y Yang, J Song, R Wei, X Tang, M Li, R Wang, Y Wang, "MixCIM: A Hybrid Computing-in-Memory Macro With Less Data-Movement and Better Memory-Reuse for Depthwise Separable Neural Networks," IEEE Journal of Solid-State Circuits, 2026.
  2. J2H Diao, H Luo, J Song, B Xu, R Wang, Y Wang, X Tang, "A Computing-in-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI," IEEE Journal of Solid-State Circuits, 2025.
  3. J3J Song, X Tang, B Xu, H Diao, H Luo, Z Wu, Y Wang, R Wang, R Huang, "A 1131-kb/mm2 14.0-to-53.3-TOPS/W 8-bit Analog-Assisted Digital Compute-in-Memory With Hybrid Local-Refresh eDRAM for Attention Computing," IEEE Journal of Solid-State Circuits, 2025.
  4. J4Z Wu, X Tang, T Zhang, L Lin, H Luo, B Xu, Z Wu, J Song, Y Liang, X Bo, ..., "SKADI: A 28-nm Complete K-SAT Solver Featuring Bidirectional In-Memory Deduction and Incremental Updating," IEEE Journal of Solid-State Circuits, 2025.
  5. J5B Xu*, J Song*, X Tang, H Luo, Z Wu, R Wang, X Bo, Y Wang, "A 0.2-V Edge-Pursuit Continuous-Time Ising Machine Using Ring-Oscillator Collapse and Delay-Enabled Positive Feedback," IEEE Journal of Solid-State Circuits, 2025. (* co-first author)
  6. J6X Qiao, Q Guo, X Tang, J Song, R Wei, M Li, R Wang, Y Wang, "A 16.38 TOPS and 4.55 POPS/W SRAM computing-in-memory macro for signed operands computation and batch normalization implementation," IEEE Transactions on Circuits and Systems I: Regular Papers 71 (4), 1706-1718, 2024.
  7. J7H Diao, Y He, X Li, C Tang, W Jia, J Yue, H Luo, J Song, X Li, H Yang, ..., "A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference," IEEE Journal of Solid-State Circuits, 2024.
  8. J8K Xiao, X Qiao, X Cui, J Song, H Luo, X Wang, Y Wang, "A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations," IEEE Transactions on Circuits and Systems II: Express Briefs 71 (7), 3263-3267, 2024.
  9. J9Z Wu, J Song, X Tang, B Xu, H Luo, Y Yang, R Wang, X Bo, Y Wang, "A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing," IEEE Journal of Solid-State Circuits, 2024.
  10. J10J Song, X Tang, X Qiao, Y Wang, R Wang, R Huang, "A 28 nm 16 kb bit-scalable charge-domain transpose 6T SRAM in-memory computing macro," IEEE Transactions on Circuits and Systems I: Regular Papers 70 (5), 1835-1845, 2023.
  11. J11J Song, X Tang, H Luo, H Zhang, X Qiao, Z Sun, X Yang, Z Wu, Y Wang, ..., "A 4-bit calibration-free computing-in-memory macro with 3T1C current-programed dynamic-cascode multi-level-cell eDRAM," IEEE Journal of Solid-State Circuits 59 (3), 842-854, 2023.
  12. J12Z Sun, Z Wang, R Wang, L Zhang, J Zhang, Z Zhang, J Song, D Wang, ..., "Investigation of the Off-State Degradation in Advanced FinFET Technology-Part I: Experiments and Analysis," IEEE Transactions on Electron Devices 70 (3), 914-920, 2023.
  13. J13K Xiao, X Cui, X Qiao, J Song, H Luo, X Wang, Y Wang, "A 28nm 32Kb SRAM computing-in-memory macro with hierarchical capacity attenuator and input sparsity-optimized ADC for 4b MAC operation," IEEE Transactions on Circuits and Systems II: Express Briefs 70 (6), 1816-1820, 2023.
  14. J14Z Sun, W Luo, Y Jiao, Z Zhang, J Song, L Zhang, Z Wang, J Zhang, ..., "Transient self-heating effects on mixed-mode hot carrier and bias temperature instability in FinFETs: Experiments and modeling," IEEE Transactions on Electron Devices 70 (11), 5528-5534, 2023.
  15. J15Z Sun, Z Wang, R Wang, L Zhang, J Zhang, Z Zhang, J Song, D Wang, ..., "Investigation of the Off-State Degradation in Advanced FinFET Technology-Part II: Compact Aging Model and Impact on Circuits," IEEE Transactions on Electron Devices 70 (3), 921-927, 2023.
  16. J16X Qiao, J Song, X Tang, H Luo, N Pan, X Cui, R Wang, Y Wang, "A 65 nm 73 kb SRAM-based computing-in-memory macro with dynamic-sparsity controlling," IEEE Transactions on Circuits and Systems II: Express Briefs 69 (6), 2977-2981, 2022.
  17. J17J Song, H Luo, X Tang, K Xu, Z Ji, Y Wang, R Wang, R Huang, "A 3T eDRAM in-memory physically unclonable function with spatial majority voting stabilization," IEEE Solid-State Circuits Letters 5, 58-61, 2022.
  18. J18Y Hu, Y Zhang, R Wang, Z Zhang, J Song, X Tang, W Qian, Y Wang, ..., "A 28-nm 198.9-TOPS/W fault-tolerant stochastic computing neural network processor," IEEE Solid-State Circuits Letters 5, 198-201, 2022.
  19. J19J Song, Y Wang, M Guo, X Ji, K Cheng, Y Hu, X Tang, R Wang, R Huang, "TD-SRAM: Time-domain-based in-memory computing macro for binary neural networks," IEEE Transactions on Circuits and Systems I: Regular Papers 68 (8), 3377-3387, 2021.

Conference Publications

  1. C1Z Wu, X Tang, T Zhang, L Lin, H Luo, B Xu, Z Wu, J Song, Y Liang, X Bo, ..., "37.5 SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability," 2025 IEEE International Solid-State Circuits Conference (ISSCC) 68, 614-616, 2025.
  2. C2MS Lee, Z Liu, A Uppal, J Song, A Paul, F Chapotot, E Tasali, Y Xu, ..., "In-Ear EEG Auditory Neurofeedback Towards Unobtrusive Sleep Enhancement," 2025 IEEE Custom Integrated Circuits Conference (CICC), 1-7, 2025.
  3. C3H Diao, H Zhang, J Song, H Luo, Y Lin, R Wang, Y Wang, X Tang, "SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support," 2025 Design, Automation & Test in Europe Conference (DATE), 1-7, 2025.
  4. C4J Leugering, S Bansal, Z Liu, J Song, B Cherif, G Cauwenberghs, "Where to cut: Efficient ADC quantization for analog in-memory computing with discrete values," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2025.
  5. C5G Gennis, B Cherif, S Bansal, J Song, J Leugering, G Cauwenberghs, "A Highly PVT Invariant Low Power Scalable Analog Dynamic Current-Mode Translinear Matrix-Vector Multiplier," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2025.
  6. C6J Song*, Z Wu*, X Tang, B Xu, H Luo, Y Yang, Y Wang, R Wang, R Huang, "30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing," 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 490-492, 2024. (* co-first author)
  7. C7H Zhang, J Song, X Gao, X Tang, Y Lin, R Wang, R Huang, "EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration," Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024.
  8. C8H Diao, H Luo, J Song, B Xu, R Wang, Y Wang, X Tang, "A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI," 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024.
  9. C9H Zhang, X Gao, Z Shen, J Song, X Cheng, X Tang, Y Lin, R Wang, ..., "SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios," 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024.
  10. C10X Qiao*, J Song*, Y Yang, R Wei, X Tang, M Li, R Wang, Y Wang, "MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks," 2024 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2024. (* co-first author)
  11. C11K Wang, M Deng, J Song, C Peng, Y Wu, Y Ren, X Wu, W Bu, Q Huang, ..., "A Novel CMOS FEOL-Embedded Asymmetrical FET for Capacitor-less and Long-Retention DRAM Based on 300mm Logic Foundry Platform," 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 13-16, 2024.
  12. C12J Song, X Tang, H Luo, H Zhang, X Qiao, Z Sun, X Yang, Y Wang, ..., "A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC," 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023.
  13. C13H Zhang, X Gao, H Luo, J Song, X Tang, J Liu, Y Lin, R Wang, R Huang, "SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility," 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023.
  14. C14Z Sun, P Cai, J Song, D Wang, Z Liu, L Zhou, T Zhu, Y Xue, Y Liu, Z Wang, ..., "Comprehensive Study of NBTI and Off-State Reliabilty in Sub-20 nm DRAM Technology: Trap Identification, Compact Aging Model, and Impact on Retention Degradation," 2023 International Electron Devices Meeting (IEDM), 1-4, 2023.
  15. C15J Song, X Tang, H Luo, K Xu, Y Wang, Z Ji, R Wang, R Huang, "Spike-CIM: A 290TOPS/W Spike-Encoding Sparsity-Adaptive Computing-in-Memory Macro with Differential Charge-Domain Integrate-and-Fire," 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022.
  16. C16J Luo, W Xu, Y Du, B Fu, J Song, Z Fu, M Yang, Y Li, L Ye, Q Huang, ..., "Energy-and area-efficient Fe-FinFET-based time-domain mixed-signal computing in memory for edge machine learning," 2021 IEEE International Electron Devices Meeting (IEDM), 19.5.1-19.5.4, 2021.
  17. C17J Song, Y Wang, X Tang, R Wang, R Huang, "A 16Kb transpose 6T SRAM in-memory-computing macro based on robust charge-domain computing," 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021.
  18. C18C Meng, Z Xiang, N Liu, Y Hu, J Song, R Wang, R Huang, W Qian, "DALTA: A decomposition-based approximate lookup table architecture," 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-8, 2021.
  19. C19K Cheng, J Song, X Zhang, Y He, R Wang, Y Wang, "A Reliability-Concerned Compute-in-Memory Behavior Model for Convolutional Neural Network," 2021 IEEE International Symposium on the Physical and Failure Analysis of ..., 2021.
  20. C20Y Zhang, X Zhang, J Song, Y Wang, R Huang, R Wang, "Parallel convolutional neural network (CNN) accelerators based on stochastic computing," 2019 IEEE International Workshop on Signal Processing Systems (SiPS), 19-24, 2019.
  21. C21Y Zhang, R Wang, X Zhang, Z Zhang, J Song, Z Zhang, Y Wang, R Huang, "A parallel bitstream generator for stochastic computing," 2019 Silicon Nanoelectronics Workshop (SNW), 1-2, 2019.
  22. C22X Zhang, J Song, Y Wang, Y Zhang, Z Zhang, R Wang, R Huang, "An energy-efficient mixed-signal parallel multiply-accumulate (MAC) engine based on stochastic computing," 2019 IEEE 13th International Conference on ASIC (ASICON), 1-4, 2019.
  23. C23Y Zhang, Z Lin, R Wang, J Song, X Zhang, Y Wang, R Huang, "Investigation on Stochastic Computing Neuron Circuit Based on FinFET Technology," 2018 14th IEEE International Conference on Solid-State and Integrated ..., 2018.

Research Experience

University of California San Diego

Postdoctoral Research Fellow, Jul. 2024 - Present

3D-Integrated Photonic-Electronic AI Accelerator

  • Co-designed a hybrid 3D photonic-electronic neural-network accelerator integrating a high-throughput photonic front-end with an RRAM-based compute-in-memory backend, enabling energy-efficient AI acceleration through heterogeneous computing across optical and electronic domains.
  • Led the circuit design of a 12nm 1T1R RRAM-based analog compute core in close collaboration with the device team, improving compute density and energy efficiency for edge AI applications.
  • Investigated advanced 3D integration strategies including TSV implementation and DBI-based die bonding, addressing interconnect bandwidth, integration density, and heterogeneous chip integration challenges for large-scale AI systems.

Peking University

Graduate Researcher and Postdoctoral Research Fellow, Sept. 2017 - Jun. 2024

Analog Compute-in-Memory Circuits for Artificial Intelligence Applications

  • Developed a calibration-free current-programmed multi-level eDRAM compute-in-memory architecture, substantially improving compute accuracy and robustness against transistor-level variations while achieving over 300 TOPS/W energy efficiency.
  • Developed a time-domain SRAM compute-in-memory macro with a dual-edge single-input computing topology, significantly improving energy efficiency and reducing area overhead for binary neural-network acceleration.

Digital Compute-in-Memory Circuits for Artificial Intelligence Applications

  • Developed an analog-assisted digital compute-in-memory architecture for Transformer attention computing, significantly reducing 8-bit digital MAC operations through low-precision analog pre-computation while improving energy efficiency up to 53.3 TOPS/W.
  • Contributed to a one-shot floating-point compute-in-memory engine with on-device fine-tuning capability, helping improve floating-point AI inference throughput and energy efficiency for edge AI applications.

Energy-Efficient Circuits and Accelerators for Combinatorial Optimization Problems

  • Developed a variation-tolerant continuous-time Ising machine with eDRAM-based spin interactions and leaked negative-feedback annealing, enabling nanosecond-scale combinatorial optimization with 15-level coefficients and energy consumption as low as 0.33 nJ.
  • Developed an edge-pursuit continuous-time Ising machine based on even-stage ring oscillators and delay-enabled positive feedback, improving solution quality and PVT robustness while achieving ultra-low-voltage operation at 0.2 V with only 12 fJ/spin energy consumption.
  • Contributed to a complete SRAM-based K-SAT solver with dual-path processing-in-memory architecture and incremental backtracking, supporting 100% solvability with 952x speedup and 3.4x10^5 energy reduction over software SAT solvers.

Design Automation for Mixed-Signal and Compute-in-Memory Circuits

  • Contributed to an end-to-end automated analog compute-in-memory design framework with automated design-space exploration, supporting automatic generation of Pareto-optimal CIM architectures while optimizing area, throughput, and energy-efficiency trade-offs across diverse AI applications.
  • Contributed to a synergistic analog routing framework considering both geometric and electrical constraints, supporting automated routing with EM/IR-drop-aware wire sizing and symmetry-aware optimization on real-world taped-out analog and mixed-signal designs.

Professional Service

Reviewer for IEEE JSSC, TCAS-I, TCAS-II, TVLSI, TCAD, TBioCAS, JxCDC, ISCAS, Microelectronics Journal, Integration, and Scientific Reports.

Personal Interests

Outside research, I enjoy playing badminton and learning guitar as a beginner. I am also a dog person and especially fond of Golden Retrievers.

Contact

Email: jis090@ucsd.edu; songjiahao@pku.edu.cn